Digital Verification Development Engineer
About the role
Job Overview: We are seeking a Verification Engineer to create test plans based on specifications and design system-level verification environments. This role involves developing and maintaining UVM-based testbenches for block and subsystem verification.
Main Responsibilities:
- Craft constrained-random stimulus, scoreboards, monitors, and coverage models using SystemVerilog.
- Enhance regression infrastructure, continuous integration processes, and internal verification methodologies.
- Drive the closure of functional and code coverage; identify coverage gaps and implement targeted tests.
- Integrate and configure Verification IP (VIP) for standard protocols.
- Support FPGA-based prototyping and pre-silicon validation with test suites.
- Conduct RTL/Gate level simulations and analyze outcomes.
- Contribute to automation of design and verification processes.
Essential Qualifications:
- Bachelor’s degree in Electronics or Computer Engineering.
- 0-3 years of experience in developing SystemVerilog-based verification environments.
- Strong knowledge of Verilog, SystemVerilog, and object-oriented programming.
- Proficient in UVM methodology with a solid grasp of functional and code coverage metrics.
- Fluent in English; skilled in Unix/Linux operating systems.
Desirable Qualifications:
- Familiarity with RTL design, synthesis, and CDC analysis.
- Experience with shell, Perl, and TCL scripting.
How to Apply: If you're ready to join a team that values your contributions, apply today at Mixel, a Silvaco company, where we prioritize employee empowerment and growth.
Summarised by JobsOnline Africa from the employer's listing. The full details are on the employer's site when you apply.